1 TP2424 06/09/99 supertex inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability indemnification insurance agreement." supertex does not assume responsibility for use of devices described and limits its liabi lity to the replacement of devices determined to be defective due to workmanship. no responsibility is assumed for possible omissions or inaccuracies. circuitry and specifications are subject to c hange without notice. for complete liability information covering this and other supertex products, refer to the supertex 1998 databook. TP2424 pre-release information ordering information features low threshold high input impedance low input capacitance fast switching speeds free from secondary breakdown low input and output leakage complementary n- and p-channel devices applications logic level interfaces C ideal for ttl and cmos solid state relays linear amplifiers power management analog switches telecom switches low threshold dmos technology these low threshold enhancement-mode (normally-off) power transistors utilize a vertical dmos structure and supertex's well- proven silicon-gate manufacturing process. this combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in mos devices. characteristic of all mos structures, these devices are free from thermal runaway and thermally induced secondary breakdown. supertexs vertical dmos fets are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. p-channel enhancement-mode vertical dmos fets package options note: see package outline section for dimensions. order number / package bv dss /r ds(on) v gs(th) i d(on) bv dgs (max) (max) (min) to-243aa* -240v 8.0 ? -2.4v -800ma TP2424n8 * same as sot-89. product supplied on 2000 piece carrier tape reels. absolute maximum ratings drain-to-source voltage bv dss drain-to-gate voltage bv dgs gate-to-source voltage 20v operating and storage temperature -55 c to +150 c soldering temperature* 300 c * distance of 1.6 mm from case for 10 seconds. to-243aa (sot-89) g d s d low threshold
2 TP2424 1235 bordeaux drive, sunnyvale, ca 94089 tel: (408) 744-0100 ? fax: (408) 222-4895 www.supertex.com 06/09/99 switching waveforms and test circuit 90% 10% 90% 90% 10% 10% pulse generator v dd r l output d.u.t. t (on) t d(on) t (off) t d(off) t f t r input input output 0v v dd r gen 0v -10v thermal characteristics package i d (continuous)* i d (pulsed) power dissipation jc ja i dr *i drm @ t a = 25 c c/w c/w to-243aa -316ma -1.9a 1.6w ? 15 78 ? -316ma -1.9a * i d (continuous) is limited by max rated t j . ? mounted on fr5 board, 25mm x 25mm x 1.57mm. significant p d increase possible on ceramic substrate. symbol parameter min typ max unit conditions bv dss drain-to-source -240 v v gs = 0v, i d = -250 a breakdown voltage v gs(th) gate threshold voltage -1.0 -2.4 v v gs = v ds , i d = -1.0ma ? v gs(th) change in v gs(th) with temperature 4.5 mv/ cv gs = v ds , i d = -1.0ma i gss gate body leakage -100 na v gs = 20v, v ds = 0v i dss zero gate voltage drain current -10.0 av gs = 0v, v ds = max rating -1.0 ma v gs = 0v, v ds = 0.8 max rating t a = 125 c i d(on) on-state drain current -0.3 v gs = -4.5v, v ds = -25v -0.8 v gs = -10v, v ds = -25v r ds(on) 10.0 ? v gs = -4.5v, i d = -150ma 8.0 v gs = -10v, i d = -500ma ? r ds(on) change in r ds(on) with temperature 0.75 %/ cv gs = -10v, i d = -500ma g fs forward transconductance 150 m v ds = -25v, i d = -200ma c iss input capacitance 200 c oss common source output capacitance 100 pf c rss reverse transfer capacitance 40 t d(on) turn-on delay time 20 t r rise time 30 t d(off) turn-off delay time 35 t f fall time 25 v sd diode forward voltage drop -1.5 v v gs = 0v, i sd = -500ma t rr reverse recovery time 300 ns v gs = 0v, i sd = -500ma notes: 1.all d.c. parameters 100% tested at 25 c unless otherwise stated. (pulse test: 300 s pulse, 2% duty cycle.) 2.all a.c. parameters sample tested. electrical characteristics (@ 25 c unless otherwise specified) a ns v dd = -25v, i d = -250ma, r gen = 25 ? v gs = 0v, v ds = -25v f = 1.0 mhz static drain-to-source on-state resistance ?
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